 |
Shadowrun: Awakened 29 September 2011 - Build 871
|
linux_intel64.h
Go to the documentation of this file.
00001 /* 00002 Copyright 2005-2010 Intel Corporation. All Rights Reserved. 00003 00004 This file is part of Threading Building Blocks. 00005 00006 Threading Building Blocks is free software; you can redistribute it 00007 and/or modify it under the terms of the GNU General Public License 00008 version 2 as published by the Free Software Foundation. 00009 00010 Threading Building Blocks is distributed in the hope that it will be 00011 useful, but WITHOUT ANY WARRANTY; without even the implied warranty 00012 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 GNU General Public License for more details. 00014 00015 You should have received a copy of the GNU General Public License 00016 along with Threading Building Blocks; if not, write to the Free Software 00017 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 00018 00019 As a special exception, you may use this file as part of a free software 00020 library without restriction. Specifically, if other files instantiate 00021 templates or use macros or inline functions from this file, or you compile 00022 this file and link it with other files to produce an executable, this 00023 file does not by itself cause the resulting executable to be covered by 00024 the GNU General Public License. This exception does not however 00025 invalidate any other reasons why the executable file might be covered by 00026 the GNU General Public License. 00027 */ 00028 00029 #ifndef __TBB_machine_H 00030 #error Do not include this file directly; include tbb_machine.h instead 00031 #endif 00032 00033 #include "linux_common.h" 00034 00035 #define __TBB_WORDSIZE 8 00036 #define __TBB_BIG_ENDIAN 0 00037 00038 #define __TBB_release_consistency_helper() __asm__ __volatile__("": : :"memory") 00039 00040 #ifndef __TBB_rel_acq_fence 00041 inline void __TBB_rel_acq_fence() { __asm__ __volatile__("mfence": : :"memory"); } 00042 #endif 00043 00044 #define __MACHINE_DECL_ATOMICS(S,T,X) \ 00045 static inline T __TBB_machine_cmpswp##S (volatile void *ptr, T value, T comparand ) \ 00046 { \ 00047 T result; \ 00048 \ 00049 __asm__ __volatile__("lock\ncmpxchg" X " %2,%1" \ 00050 : "=a"(result), "=m"(*(volatile T*)ptr) \ 00051 : "q"(value), "0"(comparand), "m"(*(volatile T*)ptr) \ 00052 : "memory"); \ 00053 return result; \ 00054 } \ 00055 \ 00056 static inline T __TBB_machine_fetchadd##S(volatile void *ptr, T addend) \ 00057 { \ 00058 T result; \ 00059 __asm__ __volatile__("lock\nxadd" X " %0,%1" \ 00060 : "=r"(result),"=m"(*(volatile T*)ptr) \ 00061 : "0"(addend), "m"(*(volatile T*)ptr) \ 00062 : "memory"); \ 00063 return result; \ 00064 } \ 00065 \ 00066 static inline T __TBB_machine_fetchstore##S(volatile void *ptr, T value) \ 00067 { \ 00068 T result; \ 00069 __asm__ __volatile__("lock\nxchg" X " %0,%1" \ 00070 : "=r"(result),"=m"(*(volatile T*)ptr) \ 00071 : "0"(value), "m"(*(volatile T*)ptr) \ 00072 : "memory"); \ 00073 return result; \ 00074 } \ 00075 00076 __MACHINE_DECL_ATOMICS(1,int8_t,"") 00077 __MACHINE_DECL_ATOMICS(2,int16_t,"") 00078 __MACHINE_DECL_ATOMICS(4,int32_t,"") 00079 __MACHINE_DECL_ATOMICS(8,int64_t,"q") 00080 00081 static inline int64_t __TBB_machine_lg( uint64_t x ) { 00082 int64_t j; 00083 __asm__ ("bsr %1,%0" : "=r"(j) : "r"(x)); 00084 return j; 00085 } 00086 00087 static inline void __TBB_machine_or( volatile void *ptr, uint64_t addend ) { 00088 __asm__ __volatile__("lock\norq %1,%0" : "=m"(*(volatile uint64_t*)ptr) : "r"(addend), "m"(*(volatile uint64_t*)ptr) : "memory"); 00089 } 00090 00091 static inline void __TBB_machine_and( volatile void *ptr, uint64_t addend ) { 00092 __asm__ __volatile__("lock\nandq %1,%0" : "=m"(*(volatile uint64_t*)ptr) : "r"(addend), "m"(*(volatile uint64_t*)ptr) : "memory"); 00093 } 00094 00095 static inline void __TBB_machine_pause( int32_t delay ) { 00096 for (int32_t i = 0; i < delay; i++) { 00097 __asm__ __volatile__("pause;"); 00098 } 00099 return; 00100 } 00101 00102 // Machine specific atomic operations 00103 00104 #define __TBB_CompareAndSwap1(P,V,C) __TBB_machine_cmpswp1(P,V,C) 00105 #define __TBB_CompareAndSwap2(P,V,C) __TBB_machine_cmpswp2(P,V,C) 00106 #define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C) 00107 #define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C) 00108 #define __TBB_CompareAndSwapW(P,V,C) __TBB_machine_cmpswp8(P,V,C) 00109 00110 #define __TBB_FetchAndAdd1(P,V) __TBB_machine_fetchadd1(P,V) 00111 #define __TBB_FetchAndAdd2(P,V) __TBB_machine_fetchadd2(P,V) 00112 #define __TBB_FetchAndAdd4(P,V) __TBB_machine_fetchadd4(P,V) 00113 #define __TBB_FetchAndAdd8(P,V) __TBB_machine_fetchadd8(P,V) 00114 #define __TBB_FetchAndAddW(P,V) __TBB_machine_fetchadd8(P,V) 00115 00116 #define __TBB_FetchAndStore1(P,V) __TBB_machine_fetchstore1(P,V) 00117 #define __TBB_FetchAndStore2(P,V) __TBB_machine_fetchstore2(P,V) 00118 #define __TBB_FetchAndStore4(P,V) __TBB_machine_fetchstore4(P,V) 00119 #define __TBB_FetchAndStore8(P,V) __TBB_machine_fetchstore8(P,V) 00120 #define __TBB_FetchAndStoreW(P,V) __TBB_machine_fetchstore8(P,V) 00121 00122 #define __TBB_Store8(P,V) (*P = V) 00123 #define __TBB_Load8(P) (*P) 00124 00125 #define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V) 00126 #define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V) 00127 00128 // Definition of other functions 00129 #ifndef __TBB_Pause 00130 #define __TBB_Pause(V) __TBB_machine_pause(V) 00131 #endif 00132 #define __TBB_Log2(V) __TBB_machine_lg(V) 00133 00134 // Special atomic functions 00135 #define __TBB_FetchAndAddWrelease(P,V) __TBB_FetchAndAddW(P,V) 00136 #define __TBB_FetchAndIncrementWacquire(P) __TBB_FetchAndAddW(P,1) 00137 #define __TBB_FetchAndDecrementWrelease(P) __TBB_FetchAndAddW(P,-1) 00138 00139 // Use generic definitions from tbb_machine.h 00140 #undef __TBB_TryLockByte 00141 #undef __TBB_LockByte
